The sampling frequency fS of an analog signal with frequency content from zero Hertz to B Hertz has to be higher than the Nyquist rate fN to avoid an aliasing effect. This can be expressed by the equation:fS≧fN=2·B 
Hence, as higher the analog input signal bandwidth B, as higher the necessary sampling rate fS. That is why applications that deal with very high analog input bandwidths B, such as Real-Time-Oscilloscopes, short RTO, call for very high sampling speeds.
Referring to WO 94/06121 A1, a high speed transient sampling unit is described. Therein, a tapped transmission line is used to propagate an input signal from an input node to an output node of the transmission line. The taps are provided with high speed sampling gates at which a distributed strobe signal is applied. Each sampling gate obtains the same distributed strobe signal without phase shifting. Therefore, at each tap of the transmission line, the same strobe signal is applied so that the sampling speed is increased.
Another method for increasing the sampling speed is shown in FIG. 1. Therein an input node is shown for applying an analog input signal IN that needs to be sampled using a so-called interleaved sampling architecture. Such an interleaved sampling architecture is for instance described in prior art document US 2013/0027234 A1. The interleaved sampling architecture is very attractive for increasing the sampling speed. Therein individual analog-to-digital converters (ADC) 1′, 1″ and 1′″ are interleaved in that the overall sampling speed of the system is increased. Thus, each ADC obtains a distinct sampling unit 2 and a distinct digitalization unit 3 on which a sampling clock 5 is provided. Thus, a time interleaving is obtained that increases the overall sampling speed of the system by operating two or more ADC in parallel. As a rule of thumb, operating N numbers of ADCs in parallel increases the system sampling rate by approximately a factor of N.
Each ADC includes a phase shifting unit 4 that is applied to delay the specific sampling clock 5 for each specific ADC. Each sampling unit 2 in front of the respective ADC thus receives the clock signal with a determined phase shift φ0, φ1, . . . , φN such that the sampling units 2 sampling moments are equidistantly spaced in time. Thus the interleaved operation is achieved that results in an effective clock signal feff. By using a clock signal of a frequency fclock an effective clock can be expressed by the equation:feff=fclock·N 
Thus, a higher sampling speed is achieved with such an architecture.
The clock timing diagram of a four times interleaved sampler is shown in FIG. 2. The sampling clock 5 is applied to the ADC 1 and provides the samples S0. The clock 5′ provides a sampling clock that is phase shifted by the phase shifter 4′ with a phase φ1 and provides the samples S1 of the input signal IN. The clock 5″ provides a sampling clock that is phase shifted by the phase shifter 4″ with a phase φ2 and provides the samples S2 of the input signal IN. The clock 5′″ provides a sampling clock that is phase shifted by the phase shifter 4′″ with a phase φ3 and provides the samples S3 of the input signal IN. The sampling clocks 5, 5′, 5″, 5′″ are time shifted by specific phase shifters 4 to obtain a higher sampling rate for the input signal IN.
Time interleaved sampling architectures relaxes a lot the power consumption of the following digitizing unit 3, 3′, 3″, 3′″ in a given technology and its comparators meta-stability caused errors.
However, the advantages of the interleaved architecture do not come without drawbacks. Various limitations and considerations must be taken into account before turning interleaving into a successful solution.
One drawback is the bandwidth limitation. Each of the sampling units 2 shown in FIG. 1, when operating alone, usually has a high analog bandwidth B. However, connecting the sampling units 2, in a tree fashion will severely reduce the overall signal bandwidth B at their inputs. The bandwidth reduction is caused by parasitic effects from the input line metal routing connecting the analog signal to each of the sampling units 2, since the metal routing comprises a specific inductance, resistance and/or capacitance. The parasitic effects cause various effects. Additionally, parasitic effects from the sampling units own inputs reduces the bandwidth B due to an additional load at the input line at all time, even though only one sampling unit 2 operates at one time. Hence, as the number N of interleaved sampling units 2 increases, the bandwidth B will degrade. As a consequence, usually the number N of interleaved sampling units 2 directly connected to the analog input IN is limited to four.
Another drawback is the clock deterministic and random phase error. If the sampling instants of time interleaved samplers are not equidistant in time, then the sampled input signal will contain errors which appear at determined frequencies in its spectrum. Furthermore, as the analog input bandwidth B increases, as the error generated by the error sampling instants increases.
The input clock signal has to be physically routed to all the sampling units 2. Additionally, each sampling unit 2 receives a phase adjusted input clock, phase shifted by the specific phase shifting units 4, 4′, 4″, 4′″. It is quite clear that with a higher number N of interleaved sampling units 2, a longer metal routing of the clock signal has to be used. This longer metal routing will reduce the bandwidth B of the clock signal until it arrives at the specific sampling unit 2. Hence, the clock signal needs further intermediate re-buffering to maintain its signal level. All the necessary clock signal re-buffering will not just introduce random source of errors in the clock signal, but will deteriorate its phase stability. This makes it more difficult to generate and maintain equally spaced sampling instants.
Assuring that each sampler receives the correct clock phase is usually done by a local phase shifting unit 4 that is applied close to the sampling unit 2. As the number N of the interleaved sampling unit 2 increases, the phase correction range increases. Thus, the complexity of the local phase shifting unit 4 increases. The phase shifting unit 4 will also add random noise sources to the clock signal and will suffer from phase instability due to temperature, processing, etc.
Another drawback is the offset and the gain error. Gain and offset mismatches between the ADC 1 outputs are parameters of concern in a time interleaved system. If one channel that comprises a specific sampling unit 2 and a respective digitizing unit 3 shows an offset and a gain error, the digitized signal represents not only the original input signal IN but also an undesired error in the digital domain. Offset discrepancy and gain mismatches show up signal spurs in the spectrum of the digitized signal.
What is therefore needed is an approach for an interleaving sampling structure for an analog-to-digital converter that increases the sampling speed without a bandwidth limitation, a clock deterministic and random phase error.